1. Field of the Invention
This invention relates to a delaying detection circuit which is employed in a receiving apparatus of a digital communication system, and used for reproduction of a digital signal from a received signal.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional delaying detection circuit which uses a binary PSK (Phase Shift Keying) signal generally employed as an input signal. In FIG. 1, reference numeral 1 is an input terminal of a received signal, 2 a delaying circuit which delays an input signal (a received signal) by one symbol time T, 8 a multiplier which performs multiplication for phase comparison between the received signal and a delay signal output from the delay circuit 2, 9 a lowpass filter for removing high frequency components, and 10 an output terminal of a demodulated data.
Next, the operation will be described. A received signal input from the input terminal 1 is represented by I(t) cos 2.pi.fct. Here, fc is a carrier frequency, and I(t) is a data. It is assumed that if the time corresponding to one symbol is represented by T, the data I(t) is A and -A in accordance with a data "0" and "1" at sample points for each T (A is a positive number). Also, it is assumed that one symbol time T can be divided by 1/fc, that is, T =n/fc (n is an integer).
The received signal is delayed by one symbol time in the delaying circuit 2 to be a delay signal. The multiplier 8 multiplies the received signal itself by the delay signal. The output of the multiplier 8 is as follows. ##EQU1##
Since the lowpass filter (LPF) 9 is set so as not to make components of cos 4.pi.ft pass therethrough, the output of the LPF is 1/2.multidot.I(t).multidot.I(t-T). Accordingly, from the output terminal 10, 1/2.multidot.I(t).multidot.I(t-T) is output. A code judgement circuit (not shown) provided in the next stage judges a code of 1/2.multidot.I(t).multidot.I(t-T). When the code is positive, the input signal and the delay signal have the same phase, by which it can be judged that the same symbol as that before one symbol has been received. When the code is negative, the input signal has a different phase from that of the delay signal, by which it can be judged that a different symbol has been received. Incidentally, though the case where the received signal is a binary PSK signal is described here, a plurality of the circuits shown in FIG. 1 are employed in the case where the received signal is a PSK signal having values not less than 4.
By the way, when one symbol time T can not be divided by 1/fc, the phase of the delay signal which is delayed by one symbol time T does not coincide with that of the received signal, the above-mentioned description does not hold. Namely, cos 2.pi.fct.noteq.cos 2.pi.fc(t-T). Here, assuming T=n/fc-.DELTA.t, the following equation holds. ##EQU2## Accordingly, in order to make the phase of the delay signal coincide with that of the received signal, it is necessary to make the delay time be T+.DELTA.t. In this time, the delay signal becomes I(t-T-.DELTA.t) cos 2.pi.fct as shown in FIG. 2. Accordingly, 1/2.multidot.I(t).multidot.I(t-T-.DELTA.t) is output as a demodulated data from the output terminal 10.
Since the conventional delaying detection circuit is constituted as described above, when one symbol tim T is not an integer multiple of the period of the carrier wave, the delay time between the received signal and the delay signal of which phase is compared with that of the received signal is not equal to one symbol time T, and consequently, there are problems that errors yield in the demodulated data and the error rate increases.